The present invention relates to a signal processing apparatus and method, and more particularly to a signal processing apparatus and method wherein a video signal of the HDTV (High Definition Television) system is down converted into another video signal of the NTSC system.
A conventionally known up-down converter typically has such a configuration as shown in FIG. 1. Referring to FIG. 1, the up-down converter generally denoted at 1 includes an A/D (Analog to Digital) converter 11 which A/D converts a video signal input thereto from an external apparatus not shown and supplies a resulting digital video signal to an interpolation circuit 14. The external apparatus further inputs a vertical synchronizing signal (in_VD) (hereinafter referred to as input vertical synchronizing signal) included in the video signal to the interpolation circuit 14 through an input terminal 12-1 and further inputs a horizontal synchronizing signal (in_HD) (hereinafter referred to as input horizontal synchronizing signal) included in the video signal to the interpolation circuit 14 and a PLL circuit 13 (Phase-Locked Loop) through another input terminal 12-2. The PLL circuit 13 produces a write system clock W_CLK synchronized with the input horizontal synchronizing signal (in_HD) input thereto through the input terminal 12-2 and outputs the write system clock W_CLK to the interpolation circuit 14.
The interpolation circuit 14 writes video data of scanning lines supplied from the A/D converter 11 into a frame memory 15 in synchronism with the write system clock W_CLK from the PLL circuit 13. Further, the interpolation circuit 14 reads out the video data written in the frame memory 15 in synchronism with a readout system clock R_CLK from an oscillator 16. Furthermore, the interpolation circuit 14 performs conversion processing of the pixel number or line number (scanning line number) for the video data read out from the frame memory 15 to perform enlargement or reduction (up or down conversion) of the video signal. A D/A (Digital to Analog) converter 17 D/A converts the video data obtained by the up or down conversion of the interpolation circuit 14 and outputs a resulting analog video signal to an external apparatus not shown.
A readout system H counter 21 of an output synchronizing signal generation circuit 18 counts the number of readout system clock signals R_CLK from the oscillator 16 and supplies the count value to a decoder 22 and a readout system V counter 23. The decoder 22 produces an output horizontal synchronizing signal (out_HD) based on the count value supplied thereto from the readout system H counter 21 and outputs the output horizontal synchronizing signal (out_HD) to the external apparatus not shown through an output terminal 19-2.
The readout system V counter 23 counts the number of H signals from the count value supplied thereto from the readout system H counter 21 and supplies the resulting count value to another decoder 24. The decoder 24 produces an output vertical synchronizing signal (out_VD) based on the count value of the H signals supplied thereto from the readout system V counter 23 and outputs the output vertical synchronizing signal (out_VD) to the external apparatus through another output terminal 19-1.
In order for the up-down converter 1 shown in FIG. 1 to output a video signal in synchronism with an output synchronizing signal of a frequency different from that of an input synchronizing signal included in the video signal, normally a method is used wherein the video signal is written into the frame memory 15 in synchronism with a write system clock W_CLK synchronized with the input horizontal synchronizing signal (in_HD) and then is read out in synchronism with a readout system clock R_CLK received from the oscillator 16.
However, the difference in period (cycle length) between the input synchronizing signal and the output synchronizing signal sometimes causes a write system line address W_ADRS into the frame memory 15 pass a readout system line address R_ADRS or causes the readout system line address R_ADRS to pass the write system line address W_ADRS conversely. Further, since the readout system H counter 21 and the readout system V counter 23 are reset each time the power supply is turned on, the phase of the output vertical synchronizing signal (out_VD) with respect to the input vertical synchronizing signal (in_VD) (FIG. 2A) varies each time the power supply is turned on as seen in FIGS. 2B to 2F.
In particular, in a field at a timing at which the power supply is turned on, even if passing does not occur by chance, since the period of the output vertical synchronizing signal (out_VD) with respect to that of the input vertical synchronizing signal (in_VD) is in a free running state, the phase of the output vertical synchronizing signal (out_VD) with respect to the input vertical synchronizing signal (in_VD) is not fixed but flows as seen in FIGS. 3A and 3B. Accordingly, the displacement in phase between the input and output vertical synchronizing signals gradually increases until passing occurs finally between the input vertical synchronizing signal (in_VD) and the output vertical synchronizing signal (out_VD) as seen in FIG. 4.
In the example of FIG. 4, reading out of an even-numbered field even1 is started at a timing at which writing of the even-numbered field even1 is not completed, and consequently, data of an odd-numbered field odd1 which have been read already are read out again from the middle.
In this manner, the interpolation circuit 14 repetitively reads out the odd-numbered field odd1 successively twice and can thereby prevent otherwise possible passing. When writing is likely to pass reading out conversely, a predetermined field is skipped without being read out.
However, when such repetitive reading out or readout skipping is performed, then the vertical relationship in interlace of input video data and the vertical relationship in interlace of output video data are reversed (video data of each line is displayed upwardly or downwardly by one line distance from the position at which the video data should originally be displayed). Thus, in order to correct the vertical relationships, a process of shifting pixels downwardly or upwardly by one line distance is performed. As a result, in the field, the image is momentarily displaced downwardly or upwardly as seen in FIG. 5.
Therefore, the input vertical synchronizing signal (in_VD) is input to the readout system V counter 23 of the output synchronizing signal generation circuit 18 as seen in FIG. 6 to reset the count value of the readout system V counter 23 for each one frame (once for each two fields) so that passing may not occur.
However, even where such a countermeasure as just described is taken, although the displacement or offset between a generation timing of the output vertical synchronizing signal (out_VD) and a generation timing of the input vertical synchronizing signal (in_VD) becomes smaller than ±1 line (1 H), since just an integral number of output horizontal synchronizing signals (out_VD) are not included within one frame of the input vertical synchronizing signal (in_VD), the line number (horizontal scanning line number) L1 of an odd-numbered field and the line number (horizontal scanning line number) L2 of an even-numbered field have different values from each other (L1≠L2) . Consequently, there is a problem that a standard interlace signal cannot be output.